The present invention relates to semiconductor integrated circuits. More particularly, the present invention relates to an architecture for communicating between a plurality of processing elements, called silicon objects, within an integrated circuit.
As transistor density in integrated circuits continues to increase, the resulting increase in processing potential is often limited due to prohibitively high development complexity, time, and cost. While traditional microprocessors and Field Programmable Gate Array (FPGA) based designs avoid high non-recurring engineering expenses, an overall lack of performance and efficiency leads to a large area and hence high per-chip cost. In certain applications, such as multi-gigabit line rate communication processing, performance constraints render these solutions unworkable.
In these types of applications, it is convenient for integrated circuit designs to have a high degree of configurability and programmability to allow the same integrated circuit design to perform a variety of different logical functions. For example, integrated circuits have been designed with a plurality of individual, programmable processing elements, which are arranged to form an array. Each processing element can be implemented to use dedicated, xe2x80x9cnearest-neighborxe2x80x9d connections to allow that processing element to communicate with the eight nearest neighbors in the array. The eight nearest neighbors are located to the north, south, east, west, northwest, northeast, southwest, and southeast of the processing element.
Although this arrangement provides a basic level of configurability, the programmability of each processing element has been limited and it is difficult for one processing element to communicate with other processing elements that are not nearest neighbors.
Improved configurable architectures are therefore desired that provide increased flexibility in communicating from one processing element to other elements in the array and increased programmability of the logic function performed by each processing element.
One embodiment of the present invention is directed to a logic array, which includes a unidirectional segmented bus and a plurality of silicon objects. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.
Another embodiment of the present invention is directed to a logic array, which includes first and second unidirectional segmented buses. Each bus includes a string of unidirectional bus segments. First and second sets of silicon objects, including at least one common silicon object, are coupled between segments in the first and second buses, respectively. The common silicon object includes first and second bus inputs coupled to respective bus segments in the first and second buses, respectively, and first and second bus outputs coupled to subsequent bus segments in the first and second buses, respectively. A logic circuit is coupled to receive a first digital value from the first bus input and generates a new digital value. A launch circuit selectively passes the first digital value from the first bus input to the first bus output, replaces the first digital value with the new digital value on the first bus output, or passes the first digital value to the second bus output.
Yet another embodiment of the present invention is directed to a method of communicating digital values between silicon objects on an integrated circuit. The method includes: coupling a first set of silicon objects between respective unidirectional bus segments in a first unidirectional segmented bus; coupling a second set of silicon objects between respective bus segments in a second unidirectional segmented bus, wherein at least one of the silicon objects is common to the first and second sets; receiving a first digital value within the common silicon object from one of the bus segments in the first bus first; generating a new digital value within the silicon object; selectively passing the first digital value from the common silicon object to another of the bus segments in the first bus; selectively replacing the first digital value with the new digital value within the common silicon object and passing the new digital value from the common silicon object to the other bus segment in the first bus; and selectively passing the first digital value from the common silicon object to one of the bus segments in the second bus.